JTAG for Boundary-scan

JTAG is the common name for the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for production-testing of printed circuit boards using boundary scan. This standards defines a 5-pin serial protocol for accessing and controlling the signal-levels on the pins of a digital circuit.
In a JTAG compliant IC, all the pins that connect to electronic logic are linked together in a set called the Boundary Scan chain. By using JTAG to manipulate the scan chain's external interface (inputs and outputs to other chips) it is possible to test for certain faults, caused perhaps by bad soldering. In external-test mode, it can disconnect the core-logic from the pins, drive the output pins by itself, and read and latch the states of the input pins. By using JTAG to manipulate its internal interface (to on-chip registers), the combinational logic can be tested. In internal-test mode, it can disconnect the core-logic from the pins, drive the core-logic input signals by itself, and read and latch the states of the core-logic output signals.
Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These cells are then connected together to form the boundary scan shift register (BSR), which is connected to a TAP controller. These registers are connected in a dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and outputs, providing direct control of the device and detailed visibility for signals.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are:

• TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.
• TCK: Test Clock. JTAG operation is synchronous to TCK. TCK is pulsed by the equipment controlling the test and not by the tested device.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). 
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

The following data registers are required for boundary-scan :

• Bypass Register - The Bypass Register consists of a single Shift Register stage which connects the TDI to the TDO with a 1-clock delay. The Bypass Register can be used to shorten the scan chain on a system when there are other devices are to be tested.
• Device Identification Register - It reads-out an identification number which is hardwired into the chip. The format of the Device Identification Register is

 

• Reset Register - The Reset Register is a Test Data Register used to reset the part. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period after releasing the Reset Register.
• Boundary Scan Register - The Boundary Scan Register has the capability of driving and observing the logic levels on the digital I/O pins. It has been explained above.

The instruction register in ATmega32 is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation :

• BYPASS - Here the TDI and TDO lines are connected to single-bit pass-through register (which passes to TDI to the TDO with a single-clock delay). This instruction allows the testing of other devices connected to the same test-loop.
• IDCODE - Optional JTAG instruction selecting the 32-bit ID-register as Data register. The ID-register consists of a version number, a device number and the manufacturer code.
• SAMPLE_PRELOAD - Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary Scan Register is selected as Data Register.
• EXTEST - Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having Off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.

That's all for now. Comments and suggestions are most welcome..

Sleep Modes of ATmega32

Sleep modes or power saving modes present in atamega32 are similar to the sleep modes available in our laptops. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. The six sleep modes available are :-

1. Idle
2. ADC Noise Reduction
3. Power-down
4. Power-save
5. Standby
6. Extended Standby

But to use these sleep modes we must first understand the MCU Control Register (MCUCR).

A register is basically a storage space of generally 1 byte whose data is used in processing by the MCU. The MCU Control Register contains control bits for power management.

• Bit 7 – SE: Sleep Enable
  The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. This can be done by the instruction MCUCR|=(1<<SE);

• Bits 6...4 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
  These bits select between the six available sleep modes :-

1. Idle Mode - When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. This is done by MCUCR|=(0<<SM0)|(0<<SM1)|(0<<SM2);
2. ADC Noise Reduction Mode - When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to continue operating (if enabled). This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. This is done by MCUCR|=(1<<SM0)|(0<<SM1)|(0<<SM2);
3. Power-down Mode - When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the External Oscillator is stopped, while the External interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after
   having been stopped. This is done by MCUCR|=(0<<SM0)|(1<<SM1)|(0<<SM2);
4. Power-save Mode - When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Powersave mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable bit in SREG is set. This is done by MCUCR|=(1<<SM0)|(1<<SM1)|(0<<SM2);
5. Standby Mode - When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. This done by MCUCR|=(0<<SM0)|(1<<SM1)|(1<<SM2);
6. Extended Standby Mode -  When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. This done by MCUCR|=(1<<SM0)|(1<<SM1)|(1<<SM2);

To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

 

So friends, that's all for now. Soon be back with another post..