JTAG is the common name for the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. It was initially devised for production-testing of printed circuit boards using boundary scan. This standards defines a 5-pin serial protocol for accessing and controlling the signal-levels on the pins of a digital circuit.
In a JTAG compliant IC, all the pins that connect to electronic logic are linked together in a set called the Boundary Scan chain. By using JTAG to manipulate the scan chain's external interface (inputs and outputs to other chips) it is possible to test for certain faults, caused perhaps by bad soldering. In external-test mode, it can disconnect the core-logic from the pins, drive the output pins by itself, and read and latch the states of the input pins. By using JTAG to manipulate its internal interface (to on-chip registers), the combinational logic can be tested. In internal-test mode, it can disconnect the core-logic from the pins, drive the core-logic input signals by itself, and read and latch the states of the core-logic output signals.
Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These cells are then connected together to form the boundary scan shift register (BSR), which is connected to a TAP controller. These registers are connected in a dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and outputs, providing direct control of the device and detailed visibility for signals.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are:
The instruction register in ATmega32 is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation :In a JTAG compliant IC, all the pins that connect to electronic logic are linked together in a set called the Boundary Scan chain. By using JTAG to manipulate the scan chain's external interface (inputs and outputs to other chips) it is possible to test for certain faults, caused perhaps by bad soldering. In external-test mode, it can disconnect the core-logic from the pins, drive the output pins by itself, and read and latch the states of the input pins. By using JTAG to manipulate its internal interface (to on-chip registers), the combinational logic can be tested. In internal-test mode, it can disconnect the core-logic from the pins, drive the core-logic input signals by itself, and read and latch the states of the core-logic output signals.
Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These cells are then connected together to form the boundary scan shift register (BSR), which is connected to a TAP controller. These registers are connected in a dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and outputs, providing direct control of the device and detailed visibility for signals.
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are:
- TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state machine.
- TCK: Test Clock. JTAG operation is synchronous to TCK. TCK is pulsed by the equipment controlling the test and not by the tested device.
- TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains).
- TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
- Bypass Register - The Bypass Register consists of a single Shift Register stage which connects the TDI to the TDO with a 1-clock delay. The Bypass Register can be used to shorten the scan chain on a system when there are other devices are to be tested.
- Device Identification Register - It reads-out an identification number which is hardwired into the chip. The format of the Device Identification Register is
- Reset Register - The Reset Register is a Test Data Register used to reset the part. A high value in the Reset Register corresponds to pulling the External Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period after releasing the Reset Register.
- Boundary Scan Register - The Boundary Scan Register has the capability of driving and observing the logic levels on the digital I/O pins. It has been explained above.
- BYPASS - Here the TDI and TDO lines are connected to single-bit pass-through register (which passes to TDI to the TDO with a single-clock delay). This instruction allows the testing of other devices connected to the same test-loop.
- IDCODE - Optional JTAG instruction selecting the 32-bit ID-register as Data register. The ID-register consists of a version number, a device number and the manufacturer code.
- SAMPLE_PRELOAD - Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary Scan Register is selected as Data Register.
- EXTEST - Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having Off-chip connections, the interface between the analog and the digital logic is in the scan chain. The contents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
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